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ParlioLedDriver

Source: ParlioLedDriver.h

ParlioPeripheral

class ParlioPeripheral
src/light/drivers/ParlioLedDriver.h:21

Inherits: LedPeripheral

Output driver: parallel WS2812B over the ESP32-P4 Parlio (Parallel IO) TX peripheral — the P4's scale path, sibling of MultiPinLedDriver.

The shared body (slicing, encode, single-shot DMA, loopback) lives in ParallelLedDriver; Parlio is the SIMPLER peripheral, so this backend adds LESS than the i80 backend:

  • NO clockPin/dcPin: Parlio generates the pixel clock itself (kClockHz), so there are no sacrificial WR/DC lines (addBusControls is empty).

  • [powerOfTwoBus()] = false: Parlio's bus width IS the pin count (any 1..16), so nothing rounds. The i80 bus is 8 or 16 bits wide whatever the pin count, and parks the lanes it doesn't need on WR. Either way the user names only the pins that drive a strand.

Prior art: the ESP32-P4 Parlio peripheral, the hpwit/FastLED parallel-WS2812 lineage — architecture studied, never copied.

Public Methods

virtual inline uint8_t lanesAvailable() const override : The number of Parlio lanes this chip provides (0 = not this chip); the orchestrator's inert-on-wrong-chip guards key off it.

virtual inline bool powerOfTwoBus() const override : Does the bus width round up to a power of two (8/16), or is it the exact pin count?

virtual inline bool loopbackFullWidth() const override : Must the loopback self-test build a full-width bus (true) or can it run on a private 1-lane unit (false)? esp_lcd i80 / MoonI80 need the full width; Parlio can do a single lane.

virtual inline LedHwBlock hwBlock() const override : Parlio is its own TX peripheral block, distinct from LcdCam/I2S — it coexists with an i80 or MoonI80 driver on the same chip (the P4 has both).

virtual inline const char * initFailMsg() const override : The status message when bus init fails on this peripheral.

virtual inline void addBusControls(ControlList &) override : No bus controls: Parlio has no sacrificial clock/DC pins (the bus rebuilds on a data-pin change alone).

virtual inline bool busControlTriggersBuild(const char *) const override : No extra bus controls, so none can trigger a rebuild.

virtual inline void recordBusPins() override : No extra pins to record (Parlio has no WR/DC).

virtual inline bool extraBusPinsCurrent() const override : No extra pins to track, so they are always current.

virtual inline bool supportsPinExpander() const override : No 74HCT595 expander on Parlio: its single-shot transfer caps at 65,535 bytes (PARLIO_LL_TX_MAX_BITS_PER_FRAME), and the ×8 fan-out frame is ~145 KB — 2.2× over.

virtual inline bool busInit(size_t frameBytes, bool wantSecondBuffer) override : Create the Parlio bus + its DMA buffer(s) sized for frameBytes on the current lanes, driving the pixel clock at kClockHz; wantSecondBuffer requests the async double-buffer's second frame buffer (allocated only if it fits).

virtual inline uint8_t * busBuffer(uint8_t i) override : DMA buffer i (0/1) the orchestrator encodes into; buffer 1 is null when the second buffer didn't fit (single-buffer mode).

virtual inline size_t busCapacity() const override : The per-buffer byte capacity (fixed at bus creation; both buffers equal).

virtual inline size_t dmaBudgetBytes() const override : The whole-frame DMA byte budget: 0 = "no bound" (PSRAM-capable).

virtual inline bool busTransmit(uint8_t i, size_t bytes) override : Kick off the autonomous transfer of the first bytes of DMA buffer i; returns whether it started.

virtual inline bool busWait(uint8_t i, uint32_t ms) override : Block up to ms for buffer i's in-flight transfer to complete.

virtual inline uint32_t busLastTransmitUs() const override : The most recent DMA transfer's wire time (µs) — the WS2812 output floor.

virtual inline void busDeinit() override : Tear down the Parlio bus and its DMA buffer.

virtual inline platform::RmtLoopbackResult busLoopback(const uint8_t * frame, size_t frameBytes, size_t dataBytes, uint8_t rowBits) override : Run the loopback self-test.

Public Static Attributes

constexpr uint32_t kClockHz = 2'666'666