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ParlioLedDriver

Source: ParlioLedDriver.h

ParlioLedDriver

class ParlioLedDriver
src/light/drivers/ParlioLedDriver.h:21

Inherits: ParallelLedDriver< ParlioLedDriver >

Output driver: parallel WS2812B over the ESP32-P4 Parlio (Parallel IO) TX peripheral — the P4's scale path, sibling of MultiPinLedDriver.

The shared body (slicing, encode, single-shot DMA, loopback) lives in ParallelLedDriver; Parlio is the SIMPLER peripheral, so this class adds LESS than the i80 driver:

  • NO clockPin/dcPin: Parlio generates the pixel clock itself (kClockHz), so there are no sacrificial WR/DC lines (addBusControls is empty).

  • kPowerOfTwoBus = false: Parlio's bus width IS the pin count (any 1..16), so nothing rounds. The i80 bus is 8 or 16 bits wide whatever the pin count, and parks the lanes it doesn't need on WR. Either way the user names only the pins that drive a strand.

Prior art: the ESP32-P4 Parlio peripheral, the hpwit/FastLED parallel-WS2812 lineage — architecture studied, never copied.

Public Methods

inline void addBusControls() : No bus controls: Parlio has no sacrificial clock/DC pins (the bus rebuilds on a data-pin change alone).

inline bool busControlTriggersBuild(constchar *) const : No extra bus controls, so none can trigger a rebuild.

inline void recordBusPins() : No extra pins to record (Parlio has no WR/DC).

inline bool extraBusPinsCurrent() const : No extra pins to track, so they are always current.

inline bool busInit(size_t frameBytes, bool wantSecondBuffer)

inline uint8_t * busBuffer(uint8_t i) : DMA buffer i (0/1) the base encodes into; buffer 1 is null when the second buffer didn't fit (single-buffer mode).

inline size_t busCapacity() const : The per-buffer byte capacity (fixed at bus creation; both buffers equal).

inline bool busTransmit(uint8_t i, size_t bytes) : Kick off the autonomous transfer of the first bytes of DMA buffer i; returns whether it started.

inline bool busWait(uint8_t i, uint32_t ms) : Block up to ms for buffer i's in-flight transfer to complete.

inline uint32_t busLastTransmitUs() const : The most recent DMA transfer's wire time (µs) — the WS2812 output floor.

inline void busDeinit() : Tear down the Parlio bus and its DMA buffer.

inline platform::RmtLoopbackResult busLoopback(constuint8_t * frame, size_t frameBytes, size_t dataBytes, uint8_t rowBits) : Run the loopback self-test.

Public Static Attributes

constexprbool kPowerOfTwoBus =

constexprbool kLoopbackFullWidth =

constexprconstchar * kInitFailMsg = "Parlio init /

constexpruint32_t kClockHz = 2'666'666

constexprbool kSupportsPinExpander = : Create the Parlio bus + its DMA buffer(s) sized for frameBytes on the current lanes, driving the pixel clock at kClockHz; wantSecondBuffer requests the async double-buffer's second frame buffer (allocated only if it fits).

Public Static Methods

constexpr static inline constexpruint8_t lanesAvailable() : The number of Parlio lanes this chip provides (0 = not this chip); the base's inert-on-wrong-chip guards key off it.