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ParlioPeripheral

Source: ParlioPeripheral.h

ParlioPeripheral

class ParlioPeripheral
src/light/drivers/ParlioPeripheral.h:18

Inherits: LedPeripheral

Output driver: parallel WS2812B over the ESP32-P4 Parlio (Parallel IO) TX peripheral, the P4's scale path and sibling of I80Peripheral.

The shared body (slicing, encode, single-shot DMA, loopback) lives in ParallelLedDriver.

Prior art: the ESP32-P4 Parlio peripheral, the hpwit/FastLED parallel-WS2812 lineage: architecture studied, never copied.

Public Methods

virtual inline uint8_t lanesAvailable() const override : Parlio lanes this chip provides; 0 makes the orchestrator's guards hold the driver inert.

virtual inline bool powerOfTwoBus() const override : Whether the bus width must round to a power of two. It need not: 1 to 16 lanes are valid.

virtual inline bool loopbackFullWidth() const override : Whether the loopback needs the full operational bus width. It does not.

virtual inline LedHwBlock hwBlock() const override : The peripheral block this backend claims, for the sibling guard.

virtual inline const char * initFailMsg() const override : What the status says when the bus will not come up.

virtual inline void addBusControls(ControlList &) override : No bus controls: Parlio has no sacrificial clock or DC pins.

virtual inline bool busControlTriggersBuild(const char *) const override : No extra bus controls, so none can trigger a rebuild.

virtual inline void recordBusPins() override : No extra pins to record (Parlio has no WR/DC).

virtual inline bool extraBusPinsCurrent() const override : No extra pins to track, so they are always current.

virtual inline bool supportsPinExpander() const override : Whether a 74HCT595 pin expander can ride this bus. On Parlio it cannot.

virtual inline bool busInit(size_t frameBytes, bool wantSecondBuffer) override : Create the Parlio bus and its DMA buffers for frameBytes, clocked at kClockHz.

virtual inline uint8_t * busBuffer(uint8_t i) override : DMA buffer i (0 or 1) the orchestrator encodes into; 1 is null in single-buffer mode.

virtual inline size_t busCapacity() const override : The per-buffer byte capacity (fixed at bus creation; both buffers equal).

virtual inline size_t dmaBudgetBytes() const override : The largest frame one transfer can carry.

virtual inline bool busTransmit(uint8_t i, size_t bytes) override : Start the autonomous transfer of the first bytes of DMA buffer i, returning whether it began.

virtual inline bool busWait(uint8_t i, uint32_t ms) override : Block up to ms for buffer i's in-flight transfer to complete.

virtual inline uint32_t busLastTransmitUs() const override : The most recent DMA transfer's wire time (us): the WS2812 output floor.

virtual inline void busDeinit() override : Tear down the Parlio bus and its DMA buffer.

virtual inline platform::RmtLoopbackResult busLoopback(const uint8_t * frame, size_t frameBytes, size_t dataBytes, uint8_t rowBits) override : Run the loopback self-test on a private 1-lane unit.

Public Static Attributes

constexpr uint32_t kClockHz = 2'666'666 : The WS2812 slot rate: 375 ns at 2.67 MHz, the same slot the LCD backend uses.

More info

Parlio is the simpler peripheral, so this backend adds less than the i80 one: it generates the pixel clock itself and its bus width IS the pin count. The user names only the pins that drive a strand.

Every control defaults to unset, because the strand is user-soldered and a hard-coded pin could drive one committed elsewhere. The P4-NANO bench uses pins 20-27 with loopbackRxPin 33, its clear GPIOs being 20-27, 32-33 and 39-48.